Synopsys to Accelerate Samsung’s 7nm Ramp with Yield Explorer Platform
Synopsys has announced an acceleration of development on its yield learning platform designed to speed up ramp up of chips made using Samsung Foundry’s 7LPP (7 nm low power plus) process and newser technologies. The Yield Explorer is a complex yield learning platform that is designed to analyze product layouts, fab data, and product test data in order to find weak spots and enable engineers to improve yields of various chips. Eventually, the Yield Explorer will be enhanced for Samsung’s 5 nm, 4 nm, and 3 nm nodes.
Production of modern chips is an extremely complex process that takes several months to accomplish and involves thousands of steps. Actual yields of chips depend on quality of their designs as well as their power and performance requirements. Therefore, to improve yields of a particular silicon chip, multiple things have to be analyzed to identify systematic yield limiters, and this is exactly what Synopsys’ Yield Explorer does.
The Yield Explorer is a complex set of programs that analyzes data from three sources using advanced machine learning and data visualization techniques. First up, Yield Explorer analyzes product design, including layout and static timings. Secondly, the complex analyzes fab data, including inspection and metrology. Thirdly, the platform considers various product test data, such as binning, system level testing.
|Synopsys' Yield Explorer at a Glance|
|Product design data||Layout, netlist, test diagnosis, static timing analysis|
|Fab data||Inspection, metrology, wafer acceptance test (WAT)|
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